Light-emitting diode and process for producing the same

ABSTRACT

The back surface of a semiconductor crystal substrate  102  which has a thickness of about 150 μm and is made of undoped GaN bulk crystal consists of a polished plane  102   a  which is flattened through dry-etching and a grinded plane  102   b  which is formed in a taper shape and is flattened through dry-etching. On about 10 nm in thickness of GaN n-type clad layer (low carrier concentration layer)  104,  about 2 nm in thickness of Al 0.005 In 0.045 Ga 0.95 N well layer  51  and about 18 nm in thickness of Al 0.12 Ga 0.88 N barrier layer  52  are deposited alternately as an active layer  105  which emits ultraviolet light and has MQW structure comprising 5 layers in total. Before forming a negative electrode (n-electrode c) on the polished plane of the semiconductor substrate a, the polished plane is dry-etched.

TECHNICAL FIELD

The present invention relates to structure of a light-emitting diode anda method for fabricating the same. More particularly, the presentinvention deeply relates to external quantum efficiency and luminousextracting efficiency.

Accordingly, the present invention is useful for a LED (light-emittingdiode) which has shorter luminous wavelength and emits blue-violet,violet, or ultraviolet light and for a method for fabricating the same.

Also, the present invention relates to a method for forming an electrodeon a grinded plane of a semiconductor substrate comprising a conductiveGroup III nitride compound semiconductor which has already beenpolished.

The present invention can be widely applied to a semiconductor device inwhich an electrode is formed directly on its semiconductor substrate.The semiconductor device having such structure may comprise alight-emitting semiconductor device such as a semiconductor laser (LD),a light-emitting diode (LED) and also a light-receiving device and apressure sensor. Concrete function and structure of those semiconductordevices may not be restricted by applying the present invention, so thepresent invention can be applied to remarkably large field.

BACKGROUND ART

The non-patent document 1 listed below discloses general technique withrespect to external quantum efficiency and luminous extractingefficiency of a light-emitting diode such as a white-light-emittingdiode and a visible light-emitting diode.

The patent document 1 listed below also discloses a light-emitting diodewhich comprises a square pyramid taper part formed at the side of ann-type semiconductor substrate. By forming such taper part, luminousextracting efficiency improves.

Generally, in a process to manufacture a light-emitting diode, a crystalgrowth substrate on which an electrode and an objective semiconductorlayer are formed is treated through crystal growth and then processed bysuch as grinding from the back surface until its thickness becomesproper to divide the semiconductor wafer into each light-emitting deviceunit excellently. And that process is generally carried out by employinga mechanical or physical process such as polishing or dicing.

As a semiconductor device in which an electrode is formed on the backsurface of the semiconductor substrate, light-emitting semiconductordevices disclosed in the patent documents 2 to 4 are well known. Such asemiconductor device comprises an n-electrode on the back surface of aconductive semiconductor substrate and a p-electrode formed on a p-typelayer and facing to the n-electrode.

As shown in the patent documents 5 and 6, when a semiconductor substratefunctions as a crystal growth semiconductor, thickness of the crystalgrowth substrate is generally about 300 μm to 800 μm. The substrate isgrinded until its thickness becomes generally from 50 μm to 150 μm anddivided into each chip (light-emitting device) unit. The grindingprocess can be carried out before or after crystal growth process ofeach semiconductor layer.

When the substrate is grinded to be too thin, the substrate itselfbecomes easy to break and the grinding process may take too much time,which is not desirable. When the substrate is too thick, it becomesdifficult to divide the semiconductor wafer into each desired shapeprecisely and surely, which is not desirable. When the semiconductorsubstrate also functions as a crystal growth substrate, generally thesemiconductor substrate frequently needs to be handled (transferoperation) before and after crystal growth process. Accordingly, inorder that the semiconductor substrate has strength to endure thathandling, the grinding process described above is usually carried outafter crystal growth process.

Accordingly, the grinding process is generally carried out untilthickness of the semiconductor substrate becomes possible or easy tohandle or thickness of the semiconductor substrate becomes about 100 μmbefore dividing process in which the semiconductor wafer is divided intoeach chip.

[Non-patent document 1] Norihide Yamada, “Primary Technologies forHigh-efficiency Visible LEDs,” Applied Physics Letters Vol. 68, No. 2(1999), pp. 0139-0145

[Patent document 1] Japanese Patent Application Laid-open No. H11-317546

[Patent document 2] Japanese Patent Application Laid-open No.2002-261014

[Patent document 3] Japanese Patent Application Laid-open No. 2001-77476

[Patent document 4] Japanese Patent Application Laid-open No.2001-102673

[Patent document 5] Japanese Patent Application Laid-open No. H7-131069

[Patent document 6] Japanese Patent Application Laid-open No. H11-163403

DISCLOSURE OF THE INVENTION

Problems to be Solved

By carrying out the physical processes described above, however, about0.1 μm to 15 μm in thickness of damaged layer whose crystal structure isdisordered (hereinafter referred to as a physically damaged layer) maybe consequently formed on the surface of a plane which is processedthrough physical conflict and impact, and the damaged layer remainsthereon. Further, the inventors of the present invention carried outseries of experiments including experimental production, examination,investigation, and verification experiment with respect to alight-emitting diode which emits violet-color light and comprises a GaNbulk crystal as a substrate, and invented that the physically damagedlayer which is consequently formed through the processes tends to absorbor diffuse light having comparatively shorter luminous wavelength, orless than 470 nm (e.g., blue-violet light, violet light, or ultravioletlight), in the device.

This problem, however, cannot be exposed or obvious when the inventorsof the present invention examined an LED emitting blue-color light orgreen-color light whose peak luminous wavelength is 470 nm or more insimilar experiments.

Generally, using a GaN for forming a crystal growth substrate is usefulto correspond or resemble physical characteristics such as latticeconstant to that of the n-type contact layer. Because the AlN substratehas comparatively larger band gap, it is useful that light once emittedfrom the emission layer may hardly be absorbed again.

When an AlGaN group free-standing crystal (hereinafter referred to as abulk crystal) is used as the crystal growth substrate, however, largeamount of light outputted form the emission layer (active layer) leaksinto the substrate because difference of refractive indexes between thesubstrate and the semiconductor crystal growth layer which decidescharacteristics of the device is too small. Accordingly, it becomes moreimportant to recover that light effectively and to extract light to theluminous extracting side effectively when the substrate is made ofmaterial such as a GaN bulk crystal. In short, that may become animportant problem to be solved in order to improve external quantumefficiency and luminous extracting efficiency of the device especiallywhen a light-emitting diode comprising a AlGaN group crystal growthsubstrate such as a GaN substrate and having comparatively shorterluminous wavelength is manufactured.

When grains in slurry (abrasives) employed in the polishing treatmentare coarse, the polished plane tends to become rough or a damaged layertends to be formed beneath the polished plane. Crystallinity of thedamaged layer is deteriorated owing to friction and pressure appliedduring the polishing treatment. Thickness of the damaged layer maydepend on each condition of slurry, frictional force, and pressure, butthe inventors of the present invention conducted some experiments andfound that the damaged layer may generally have thickness from 0.1 μm to10 μm.

FIGS. 4A and 4B show sectional views of the damaged layer which isproduced through such polishing treatment. The polishing treatment iscarried out by using slurry each of whose grain is 9 μm. FIG. 4A is animage observed through a scanning electron microscopy (SEM image) andFIG. 4B is a monochrome image through an electron beam luminescence (CLimage). As shown in FIGS. 4A and 4B, 1 μm or more in thickness of thedamaged layer with deteriorated crystallinity is formed below thepolished plane.

The damaged layer becomes an obstacle to improve contact between thepolished plane and an electrode deposited afterward, and interference ofthe damaged layer prevents from obtaining excellent ohmic contact. Thatresults in unnecessarily raising driving voltage of the semiconductordevice.

In order to smooth the polished plane or to form the damaged layer whichtends to be formed during polishing treatment thinner, it is preferableto reduce each amount of slurry, frictional force, and pressure inpolishing treatment. Actually, however, reducing each amount of slurry,frictional force, and pressure in polishing treatment may take too muchtime to carry out polishing treatment, and that cannot be a practicalway to produce industrial products.

The present invention has been accomplished in an attempt to solve theaforementioned problems, and an object of the present invention is toprovide higher external quantum efficiency and higher luminousextracting efficiency of a light-emitting diode (LED) which comprises abulk crystal such as GaN as a crystal growth substrate and hascomparatively shorter luminous wavelength.

Anther object of the present invention is to reduce driving voltage of asemiconductor device effectively.

Further, another object of the present invention is to reduce the timeof polishing treatment as much as possible.

Here, each object listed above may be enough to be fulfilledindividually by at least one of each method described above, and eachinvention in the present application is not necessarily secure thatthere is a solution which solves all the problems at once.

Means to Solve the Problems

In order to solve the above-described problems, the following methodsmay be effective.

That is, the invention drawn to a first feature provides a method forfabricating a light-emitting diode of a surface emitting type in which asemiconductor layer is deposited on a crystal growth plane of a crystalgrowth substrate, comprising steps of: a shaping process for forming atleast one of an output plane and a reflection plane which contributes toluminous output of the device through polishing treatment, dicingtreatment, and blasting treatment from the back surface of the crystalgrowth substrate; and a finishing process for finishing at least one ofthe output plane and the reflection plane by further carrying outetching treatment.

Here, depth of the etching treatment may preferably be in a range from0.1 μm to 15 μm, and further preferably in a range from 0.2 μm to 8 μm.Further preferably, depth of etching may be in a range 1 μm to 7 μm. Thecrystal growth substrate may be made of a well-known material.

The invention drawn to a second feature is that the shaping processcomprises a taper part forming process for forming a taper plane, whichinclines to the crystal growth plane of the crystal growth substrate, atleast as a portion of the output plane or at least as a portion of thereflection plane.

The invention drawn to a third feature is that at least a portion of thetaper part forming process comprises a process for forming anapproximately V-shaped dividing groove which divides a semiconductorwafer comprising plural light-emitting diodes into each light-emittingdiode.

The invention drawn to a fourth feature is that the peak luminouswavelength of the light-emitting diode is less than 470 nm.

The invention drawn to a fifth feature is that the crystal growthsubstrate is formed by using Al_(x)Ga_(1-x)N (0≦x≦1) or silicon carbide(SiC).

The invention drawn to a sixth feature provides a light-emitting diodeof a surface emitting type in which a semiconductor layer is depositedon a crystal growth plane of a crystal growth substrate, wherein thecrystal growth substrate comprises at least one of an output plane and areflection plane which contributes to luminous output of the devicethrough a physical forming process such as polishing treatment, dicingtreatment, and blasting treatment, and a physically damaged layer whichis formed on the surface of at least one of the output plane and thereflection plane and remains owing to friction and shock generated inthe shaping process is removed.

The invention drawn to a seventh feature is that a metal layer which haslight-transparency to transmit light to the luminous extracting side ofthe device is formed on the output plane.

The invention drawn to an eighth feature is that a metal layer whichreflects light to the luminous extracting side of the device is formedon the reflection plane.

The invention drawn to a ninth feature is that the crystal growthsubstrate is formed by using Al_(x)Ga_(1-x)N (0≦x≦1) or silicon carbide(SiC).

The invention drawn to a tenth feature is that a taper plane whichinclines to the crystal growth plane of the crystal growth substrate isformed at least as a portion of the output plane and at least as aportion of the reflection plane.

The invention drawn to an eleventh feature provides a light-emittingdiode of a surface emitting type in which a semiconductor layer isdeposited on a crystal growth plane of a crystal growth substrate,comprising a taper plane which inclines to the crystal growth plane ofthe crystal growth substrate which is formed at least at a portion ofthe sidewall of the light-emitting diode, wherein the taper plane isexposed to the surface side of the light-emitting diode at which asemiconductor crystal layer and a positive electrode are formed, and aphysically damaged layer which is formed on the surface of the taperplane and remains owing to friction and shock generated in the taperpart forming process is removed.

The invention drawn to a twelfth feature provides a light-emitting diodewhich is fabricated by dividing a semiconductor wafer comprising plurallight-emitting diodes into each light-emitting diode, comprising a taperplane at least at a portion of the sidewall of the light-emitting diode,wherein the taper plane is a portion of the plane of an approximatelyV-shaped dividing groove which divides the semiconductor wafer into eachlight-emitting diode.

The invention drawn to a thirteenth feature is that the peak luminouswavelength of the light-emitting diode is less than 470 nm.

The invention drawn to a fourteenth feature is to carry out dry-etchingtreatment to a polished plane of a semiconductor substrate which isalready polished and comprises a Group III nitride compoundsemiconductor before electrode forming process for forming an electrodeon the polished plane of the semiconductor substrate.

As used herein, the term “Group III nitride compound semiconductor”generally refers to a binary, ternary, or quaternary semiconductorhaving arbitrary compound crystal proportions and represented byAl_(1-x-y)Ga_(y)In_(x)N (0≦x≦1, 0≦y≦1, 0≦1-x-y≦1). A semiconductor dopedwith p-type or n-type impurity is also included in a Group III nitridecompound semiconductor described in the present specification.

The expression “Group III nitride compound semiconductor” encompassessemiconductors in which the aforementioned Group III element (Al, Ga, orIn) is partially substituted by boron (B) or thallium (Tl), or in whichnitrogen (N) is partially substituted by phosphorus (P), arsenic (As),antimony (Sb), or bismuth (Bi).

As the aforementioned p-type impurity (acceptor), a well-known p-typeimpurity such as magnesium (Mg) and calcium (Ca) may be used.

As the aforementioned n-type impurity (donor), a well-known n-typeimpurity such as silicon (Si), sulfur (S), selenium (Se), tellurium(Te), and germanium (Ge) may be used.

These impurities (acceptor or donor) may be incorporated in combinationof two or more species, and both a p-type impurity and an n-typeimpurity may be incorporated in combination.

Accordingly, by dry-etching the polished plane before forming theelectrode thereon, the damaged layer having deteriorated crystallinitycan be removed and the surface of the polished plane becomescomparatively smooth. That enables to obtain excellent ohmic contact.That may be because the damaged layer has higher resistivity owing toits deteriorated crystallinity.

Through employment of the aforementioned features of the presentinvention, driving voltage of the semiconductor device can be reducedeffectively.

In the present invention, dry-etching is carried out by using RIEequipment and ICP equipment in order to etch only a predetermined planeselectively.

According to the features described above, it is not especially requiredto dimension of grains of slurry, each amount of frictional force andpressure in polishing treatment, which enables to reduce polishing timeof the semiconductor substrate. Accordingly, by employing the method ofthe present invention, productivity of the semiconductor device can beimproved.

The invention drawn to a fifteenth feature is to form the semiconductorsubstrate by using an n-type Al_(x)Gal_(1-x)N (0≦x≦1).

FIG. 5 is a graph showing the relationship between a depth D ofdry-etching the polished plane of the semiconductor substrate comprisinga gallium nitride (n-type GaN) which is doped with Si at concentrationof 4×10¹⁸/cm³ and ohmic characteristic of the device. By varying thedepth D of dry-etching to 0 μm, 1 μm, and 4 μm, voltage and electriccurrent characteristic of the device is measured.

Measurement is carried out as shown in FIGS. 6 and 7. An n-electrode cis formed the polished plane of a semiconductor substrate a throughdeposition. A crystal growth layer b may be formed to have arbitrarystructure according to structure of a desired semiconductor device. Anarbitrary crystal growth method may be employed to grow the crystalgrowth layer b. FIG. 7 illustrates that a damaged layer a1 is removedthrough dry-etching treatment. The distance between two n-electrodes cshown in FIGS. 6 and 7 is about 100 μm, respectively. A measuringequipment y comprises a direct current power source of variable voltage,a voltage measuring apparatus and an electric current measuringapparatus, which are abbreviated in FIGS. 6 and 7.

FIG. 5 shows result of measuring electric current and voltage aftercarrying out polishing treatment using about 9 μm of grains of slurry.As shown in the graph of FIG. 5, ohmic characteristic of the n-electrodec becomes remarkably bad when dry-etching is not carried out. When thelight-emitting semiconductor device is manufactured according to thefirst feature described above, the semiconductor substrate may bepreferably formed by using an n-type Al_(x)Ga_(1-x)N (0≦x≦1) as shown inFIGS. 5, 6, and 7. In other words, the method of the second feature ofthe present invention is very preferable for at least forming theelectrode on the back surface of the substrate of the light-emittingsemiconductor device.

Especially, when the semiconductor substrate a is formed by using asemiconductor comprising Al_(x)Ga_(1-x)N (x≈0) which is doped with ann-type impurity such as Si, or by using an n-type gallium nitride,physical conditions such as hardness, lattice constant, crystallinity,and electrical conduction characteristic may be desirable. That enablesthe semiconductor substrate to function excellently as a semiconductorcrystal growth substrate and an n-type contact layer, which is verydesirable.

The invention drawn to a sixteenth feature is that depth of removing thepolished plane through dry-etching treatment is in a range from 0.1 μmto 15 μm.

Although it depends on each condition of grains of slurry, frictionalforce and pressure, the device of the present invention may functioneffectively at the depth disclosed in the sixteenth feature of thepresent invention. When the depth of removing the polished plane is toolarge, dry-etching treatment takes too much time, which is notdesirable. When the depth of removing the polished plane is too small,effect for carrying out dry-etching treatment is inadequate andexcellent ohmic contact cannot be obtained, which is not desirable.Also, when the depth of removing the polished plane is too small, itbecomes necessary to reduce radius of grain of slurry, each amount offrictional force and pressure in order to obtain certain degree ofexcellent ohmic contact. That requires too much time to carry outpolishing treatment, which is not desirable.

The invention drawn to a seventeenth feature is that depth of removingthe polished plane through dry-etching treatment is in a range from 0.2μm to 8 μm.

Although it depends on each condition of slurry, frictional force,pressure, and composition ratio of the substrate, optional depth ofdry-etching the polished plane may be within the range disclosed in theseventeenth feature of the present invention. That is, when the depth ofdry-etching the polished plane is in that range, both polishingtreatment and dry-etching treatment can be carried out in their minimumtime and optimum ohmic characteristic can be obtained between thesemiconductor substrate and the electrode.

Through employment of the aforementioned features of the presentinvention, the aforementioned drawbacks can be overcome effectively andrationally.

EFFECTS OF THE INVENTION

Effects to be obtained by the present invention are as follows.

That is, according to the first feature of the present invention, whenan objective shaping process is carried out through mechanical orphysical treatments such as polishing, dicing, and blasting treatments,the physically damaged layer left on the surface of at least one of theoutput plane and the reflection plane (hereinafter referred to as aphysically processed plane or simply a processed plane) can be removedeffectively through etching treatment. As a result, light absorption ordiffusion of light toward inside of the device caused by the physicallydamaged layer formed on the processed plane (: the output plane or thereflection plane) can be restrained effectively. Accordingly, externalquantum efficiency and luminous extracting efficiency can be improvedwhen the light-emitting diode (LED) is manufactured.

According to the second feature of the present invention, because amountof light absorbed by the sidewalls of the light-emitting diode ordiffused in the diode increases owing to the method of the first featureof the present invention, external quantum efficiency and luminousextracting efficiency of the light-emitting diode can be improvedeffectively.

Also, by carrying out the taper part forming process during the shapingprocess, not only the taper part but also the physically processed planeincluding the taper part can be etched at one time. In short, thefinishing process for etching the processed plane can be carried outalong with etching the taper part.

According to the third feature of the present invention, at least aportion of the taper part forming process can be carried out by carryingout the process for forming the dividing groove. Alternatively, theprocess for forming the dividing groove may take place of the wholeprocess for forming the taper part. As a result, the taper part formingprocess can be carried out quite effectively according to the thirdfeature of the present invention.

Especially, each feature of the present invention described above mayfunction effectively with respect to a light-emitting diode at least aportion of whose luminous emission is in a frequency range whoseluminous spectrum is at least less than 470 nm. According to the fourthand thirteenth aspects of the present invention, however, large amountof light whose luminous spectrum is less than 470 nm in a frequencyrange of the objective luminous spectrum of the light-emitting diode maynot have bad influence, or absorption of light or diffusion of light inthe device, owing to the physically damaged layer. As a result,according to the fourth and thirteenth aspects of the present invention,a light-emitting diode with high luminous efficiency, in whichpossibility of reducing external quantum efficiency owing to thephysically damaged layer is effectively excluded, can be provided.

Here, the threshold of the luminous spectrum (470 nm) is determined fromsome experience as described above. Also, this threshold may partiallydepend on degree of damage (depth of roughness) of the physicallydamaged layer, material and characteristic of the semiconductor crystal(a growth layer or a semiconductor bulk crystal substrate), and so on.Degree of damage or depth of roughness of the physically damaged layermay depend on material and diameter of a grain of slurry used in thepolishing treatment, material, diameter of a grain, momentum and flowrate of slurry used in the blasting treatment, and so on. Evenconsidering all those condition, however, the present invention is foundto be effective at least under the scope described above.

The crystal growth substrate of the present invention can be made ofwell-known and arbitrary materials. Alternatively, considering devicecharacteristics such as luminous extracting efficiency with respect torefraction index and light transparency, the crystal growth substratemay preferably be made of semiconductor bulk crystal such as an AlGaNgroup composition or a SiC group composition in order to improveluminous output of the light-emitting diode as much as possible (thefifth and the ninth features of the present invention). Effect of thepresent invention becomes more remarkable when the substrate is made ofa material which has comparatively good characteristic with respect toluminous extracting efficiency as described above.

Especially, using a GaN for forming a crystal growth substrate is usefulto correspond or resemble physical characteristics such as latticeconstant to those of the n-type contact layer. Because the AlN substratehas comparatively larger band gap, the light once emitted from theemission layer may hardly be absorbed again in AlN, and that isdesirable. Here, aluminum composition x of Al_(x)Ga_(1-x)N (0≦x≦1)functions as an adjustable parameter which is very optimum to select,add, or weight superiority of each condition (the fifth and the ninthfeatures of the present invention).

According to the sixth feature of the present invention, because thephysically damaged layer is removed, absorption of light (or diffusionof light to inside of the device) owing to the physically damaged layercan be restrained effectively. That is, according to the sixth featureof the present invention, an objective light-emitting diode (LED) canobtain higher external quantum efficiency and higher luminous extractingefficiency.

According to the seventh feature of the present invention, a metal layerwhich has light-transparency to transmit light to the luminousextracting side of the device is formed on the output plane. As aresult, absorption of light at the light-transparent plane can bereduced and luminous transparency around the metal layer is improved.That results in improving external quantum efficiency and luminousextracting efficiency of the device.

According to the eighth feature of the present invention, a metal layerwhich reflects light is formed on the reflection plane. As a result,absorption of light at the reflection plane can be reduced andreflectivity of the reflection plane can be improved. That results inimproving external quantum efficiency and luminous extracting efficiencyof the device.

According to the tenth feature of the present invention, quantity oflight which is absorbed at the sidewalls of the light-emitting diode oris diffused in the light-emitting diode can be reduced effectively andthe reflected light can be outputted to the luminous extracting sidevery effectively. As a result, external quantum efficiency and luminousextracting efficiency of the device can be improved.

According to the eleventh feature of the present invention, the taperplane is exposed to the surface of the device. That enables to improveexternal quantum efficiency and luminous extracting efficiency of thelight-emitting diode effectively when light radiated from the taperplane is outputted directly to the surface of the light-emitting diode.

And the taper plane can be formed by using a portion of the planecomprising a dividing groove which is formed on the surface of thedevice (the twelfth feature of the present invention). At that time, anyparticular process for forming a taper part is not needed, and that isvery desirable.

According to the thirteenth feature of the present invention, thepolished plane for forming the electrode is dry-etched and then theelectrode is formed on the etched plane. Because the damaged layer canbe removed through polishing treatment, ohmic characteristic of theelectrode toward the polished plane can be improved.

According to the fourteenth feature of the present invention, when thesemiconductor substrate is made of an n-type Al_(x)Ga_(1-x)N (0≦x≦1),ohmic characteristic of the electrode can be remarkably improved bycarrying out dry-etching treatment on the polished plane before formingthe electrode thereon.

According to the fifteenth feature of the present invention, when thedepth of dry-etching, or the thickness of the polished plane to beremoved, is in a range from 0.1 μm to 15 μm, time for the polishingprocess and the dry-etching process can be kept the minimum and ohmiccharacteristic of the electrode can be improved maximally.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a sectional view of a face-down type light-emitting diode 100according to a first embodiment of the present invention.

FIG. 2 is a sectional view of a face-up type light-emitting diode 200according to a second embodiment of the present invention.

FIG. 3 is a sectional view of a face-up type light-emitting diode 1000according to a third embodiment of the present invention.

FIGS. 4A and 4B are photos of sectional planes of damaged layersgenerated through a grinding process.

FIG. 5 is a graph showing the relationship between ohmic characteristicand a depth of dry-etching a grinded plane.

FIG. 6 is a schematic view of a circuit for measuring ohmiccharacteristic of the face-up type light-emitting diode 200 shown inFIG. 2.

FIG. 7 is a schematic view of a circuit for measuring ohmiccharacteristic of the face-up type light-emitting diode 200 shown inFIG. 2.

FIG. 8 is a sectional view of a light-emitting diode 500 according tothe embodiment of the present invention.

FIG. 9 is a table showing each driving voltage VF of the light-emittingdiode 500 according to the embodiment and a light-emitting diode 500′according to a modified embodiment of the present invention.

FIGS. 10A-10C are views illustrating each process for fabricating thelight-emitting diode according to other embodiment of the presentinvention.

BEST MODE FOR CARRYING OUT THE INVENTION

The present invention can show excellent actions and effects under thefollowing conditions.

For example, the depth of etching may preferably be in a range from 0.1μm to 15 μm, and more preferably from 0.2 μm to 8 μm. And because thedamaged layer has a thickness of 1 μm or more, the depth of etching maymore preferably be in a range from 1 μm to 7 μm. When the depth ofetching is too small, a physically damaged layer often tend not to beremoved sufficiently. When the depth of etching is too large, too muchtime is needed for the etching treatment and it is undesirable inproductivity and production cost. That is, according to this appropriaterange of the depth of etching, the physically damaged layer remaining ona plane which is etched physically can be removed sufficiently to therequired content.

More preferably, suitable and optimum depth of etching may be determinedaccording to actual and physical conditions of shaping. For example,although the required and sufficient depth of etching depends on eachcondition such as a size of slurry, pressure of the process plane in agrinding process and its processing speed, the appropriate depth ofetching may be determined experientially without any particulartrial-and-error process. That can be applied to other mechanical shapingprocesses such as dicing and blasting.

Materials for forming the crystal growth substrate and impurities dopedinto it are already described above.

Especially, the crystal growth substrate made of GaN is useful, forexample, for each physical characteristic such as lattice constant tomatch or to correspond to that of the n-type contact layer. Also, theAlN substrate is useful because it hardly absorbs the light emittedagain owing to its comparatively larger bandgap. In order to select,add, or weight each advantage or usefulness properly, aluminumcomposition ratio x in the composition formula Al_(x)Ga_(1-x)N (0≦x≦1)can be a very optimum adjustable parameter. And especially when an LEDwhich emits light having very short wavelength is manufactured, bandgap,or aluminum composition ratio x, of each semiconductor crystal layer ofthe LED may preferably be as large as possible, as long as it does notaffect other characteristics in the LED.

Alternatively, the active layer (the emission layer) in thelight-emitting diode may have arbitrary structure. It may have MQWstructure, SQW structure, or single-layer structure which does not havequantum-well structure.

Embodiments of the present invention will next be described based onconcrete examples. The scope of the present invention, however, is notlimited to the embodiment described below.

Embodiment 1

FIG. 1 is a sectional view of a face-down type light-emitting diode 100of the present embodiment. The back surface of a semiconductor crystalsubstrate 102 which has a thickness of about 150 μm and is made ofundoped GaN bulk crystal comprises a polished plane 102 a which isflattened through dry-etching and a polished plane 102 b which is formedin a taper shape and is flattened through dry-etching. As a crystalgrowth plane which is almost parallel to the polished plane 102 a of thesemiconductor crystal substrate 102, c plane of the GaN bulk crystal isapplied. About 4.0 μm in thickness of silicon (Si) doped gallium nitride(GaN) n-type contact layer 103 is deposited through crystal growth onthe crystal growth plane.

The n-type contact layer 103 has an impurity (Si) concentration of about1×10¹⁹/cm³. About 10 nm in thickness of GaN n-type clad layer (lowcarrier concentration layer) 104 is formed on the n-type contact layer103.

On the n-type clad layer 104, about 2 nm in thickness ofAl_(0.005)In_(0.045)Ga_(0.95)N well layer 51 and about 18 nm inthickness of Al_(0.12)Ga_(0.88)N barrier layer 52 are depositedalternately as an active layer 105 which emits ultraviolet light and hasMQW structure comprising 5 layers in total. About 50 nm in thickness ofp-type clad layer 106 made of Mg-doped p-type Al_(0.15)Ga_(0.85)N isformed on the active layer 105. About 100 nm in thickness of p-typecontact layer 107 made of Mg-doped p-type GaN is formed on the p-typeclad layer 106.

On the p-type contact layer 107, a positive electrode 120 havingmultiple-layer structure is formed through metal deposition, and anegative electrode 140 is formed on the n-type contact layer 103 havinghigh-carrier concentration. The positive electrode 120 havingmultiple-layer structure comprises 3 layers in total, or a first layer121 of the positive electrode which contacts to the p-type contact layer107, a second layer 122 of the positive electrode formed on the firstlayer 121 of the positive electrode, and a third layer 123 of thepositive electrode formed on the upper portion of the second layer 122of the positive electrode.

The first layer 121 of the positive electrode is about 0.1 μm inthickness of metal layer which is made of rhodium (Rh) and contacts tothe p-type contact layer 107. The second layer 122 of the positiveelectrode is about 1.2 μm in thickness of metal layer made of gold (Au).The third layer 123 of the positive electrode is about 20 Å in thicknessof metal layer made of titanium (Ti).

The negative electrode 140 having multiple-layer structure comprisesabout 175 Å in thickness of vanadium (V) layer 141, about 1000 Å inthickness of aluminum (Al) layer 142, about 500 Å in thickness ofvanadium (V) layer 143, about 5000 Å in thickness of nickel (Ni) layer144, and about 8000 Å in thickness of gold (Au) layer 145 deposited insequence on the exposed portion of the n-type contact layer 103.

Between the thus-obtained positive electrode 120 and the negativeelectrode 140, a protection film 130 made of SiO₂ film is formed. Theprotection film 130 covers a portion of the n-type contact layer 103which is exposed to form the negative electrode 140, the sidewall of theactive layer 105 which is exposed through etching treatment, the exposedsidewall of the p-type clad layer 106, the exposed sidewall and aportion of the upper surface of the p-type contact layer 107, thesidewall of the first layer 121 of the positive electrode, the sidewallof the second layer 122 of the positive electrode, and the sidewall anda portion of the third layer 123 of the positive electrode. Thickness ofthe SiO₂ protection film 130 covering the third layer 123 of thepositive electrode is 0.5 μm.

Next, a method for manufacturing the light-emitting diode 10 isexplained hereinafter.

The light-emitting diode 10 of the present invention was producedthrough metal-organic vapor phase epitaxy (hereinafter called “MOVPE”).The following gasses were employed: ammonia (NH₃), carrier gas (H₂ orN₂), trimethylgallium (Ga(CH₃)₃, hereinafter called “TMG”),trimethylaluminum (Al(CH₃)₃, hereinafter called “TMA”), trimethylindium(In(CH₃)₃, hereinafter called “TMI”), and cyclopentadienylmagnesium(Mg(C₅H₅)₂, hereinafter called “Cp₂Mg”).

The undoped GaN bulk crystal semiconductor crystal substrate 102 wasplaced on a susceptor in a reaction chamber for the MOVPE treatmentafter its main surface ‘c’ was cleaned by an organic washing solvent andheat treatment. Thickness of the semiconductor crystal substrate 102 wasabout 400 μm. Then the semiconductor crystal substrate 102 was baked atabout 1150° C. under H₂ vapor fed into the chamber under normalatmospheric pressure.

(Growth of the N-Type Contact Layer 103)

About 4.0 μm in thickness of GaN n-type contact layer 103 havingelectron concentration of 2×10¹⁸/cm³ and Si concentration of 1×10¹⁹/cm³was formed under conditions controlled by keeping the temperature of thesemiconductor crystal substrate 102 at 1150° C., and concurrentlysupplying H₂, NH₃, TMG and dilute silane.

(Growth of the N-Type Clad Layer 104)

About 10 nm in thickness of GaN n-type clad layer 104 (low carrierconcentration layer) was formed under conditions controlled by keepingthe temperature of the semiconductor crystal substrate 102 at 1150° C.,and concurrently supplying H₂, NH₃, and TMG.

(Growth of the Active Layer 105)

After forming the n-type clad layer 104, the active layer of MQWstructure, comprising 5 layers in total, is formed.

First, about 2 nm in thickness of Al_(0.005)In_(0.045)Ga_(0.95)N welllayer 51 was formed on the n-type clad layer 104 under conditionscontrolled by lowering the temperature of the semiconductor crystalsubstrate 102 to 770° C., changing carrier gas from H₂ to N₂, keepingthe supplying amount of the carrier gas N₂ and NH₃, and concurrentlysupplying TMG, TMI, and TMA.

Next, about 18 nm in thickness of Al_(0.12)Ga_(0.88)N barrier layer 52was formed on the well layer 51 under conditions controlled byconcurrently supplying N₂, NH₃, TMG, and TMA.

By repeating these processes, the well layer 51 and the barrier layer 52were formed alternately and the active layer 105 comprising 5 layers intotal (the well layer 51, the barrier layer 52, the well layer 51, thebarrier layer 52, and the last well layer 51) was obtained.

(Crystal Growth of the P-Type Clad Layer 106)

Then magnesium (Mg) doped p-type Al_(0.15)Ga_(0.85)N having thickness ofabout 20 nm and Mg concentration of 5×10¹⁹/cm³ was formed as a p-typeclad layer 106 under conditions controlled by raising the temperature ofthe semiconductor crystal substrate 102 to 890° C. and concurrentlysupplying N₂, TMG, TMA, and CP₂Mg.

(Crystal Growth of the P-Type Contact Layer 107)

Then Mg-doped p-type GaN having thickness of about 85 nm and Mgconcentration of 5×10¹⁹/cm³ was formed as a p-type contact layer 107under conditions controlled by raising the temperature of thesemiconductor crystal substrate 102 to 1000° C., changing the carriergas to H₂ again, and concurrently supplying H₂, NH₃, TMG, and CP₂Mg.

The processes described above are the crystal growth process of eachsemiconductor layer comprising a Group III nitride compoundsemiconductor.

(Forming the Positive Electrode 120)

A photoresist layer was then formed on the surface of the wafer. Theportion of the photoresist layer above the electrode forming part of thep-type contact layer 107 was then removed by patterning usingphotolithography to form a window. In short, only a portion of thep-type contact layer 107 for forming the positive electrode 120 wasexposed. After establishing a high vacuum of less than 10⁻⁴ Pa vacuumorder, about 0.1 μm in thickness of positive electrode first layer 121made of rhodium (Rh), about 1.2 μm in thickness of positive electrodesecond layer 122 made of gold (Au), and about 20 Å in thickness ofpositive electrode third layer 123 made of titanium (Ti) were depositedin sequence on the exposed portion of the p-type contact layer 107. Thesample was then removed from the vacuum evaporation equipment and eachmetal layer laminated on the photoresist layer were removed by alift-off process.

Then the negative electrode 140 and the protection film 130 were formedaccording to each process for forming the conventional and well-knownface-down type light-emitting diode.

(Alloying Treatment)

Next, the chamber in which the resultant sample was placed was evacuatedby use of a vacuum pump, and subsequently O₂ gas was fed to the chamber,to thereby regulate the pressure of the chamber to 3 Pa. Thereafter, thetemperature of the chamber was maintained at about 550° C., and thesample was heated for about three minutes, to thereby lower theresistances of the p-type contact layer 107 and the p-type clad layer106, as well as to perform alloying of the contact layer 107 and thepositive electrode 120 and alloying of the n-type contact layer 103 andthe negative electrode 140. Thus, the electrodes can be connected toeach semiconductor layer on which both the positive and the negativeelectrodes were deposited more firmly.

(Polishing Treatment)

Next, a protection film which protects each electrode and each depositedsemiconductor layer from pressure and impact during polishing treatmentwas formed on the surface (face plane) of the wafer, and the wafer waspasted on a wafer pasting board of a polishing equipment. And the backsurface of the semiconductor crystal substrate 102 was polished by usinga polishing machine. Diameter of grains of the slurry employed in thispolishing treatment was 9 μm, and the polishing treatment was carriedout until thickness of the semiconductor crystal substrate 102 decreasedfrom 400 μm to 150 μm. Then the wafer was removed from the wafer pastingboard of the polishing equipment and washed to remove wax and theprotection film which were used to paste the wafer.

Diameter of the grains of the slurry employed in the polishing treatmentmay preferably in a range from 0.5 μm to 15 μm. When the diameter of theslurry is too big, thickness of the damaged layer tends to become toolarge, which is not desirable. When the diameter of the grains of theslurry is too small, the polishing treatment tends to take too muchtime, which is not desirable. More preferably, the diameter of thegrains of the slurry is in a range from 1 μm to 9 μm.

(Forming a Taper Part)

The wafer was pasted to an adhesive tape so that the electrode formingplane faced the adhesive tape. Next, a V-shaped groove was formed incross stripes pattern per each unit on the back surface of the wafer bycarrying out grinding process using a dicing cutter. Accordingly, agrinded plane 102 b in a taper shape as shown in FIG. 1 can be obtained.Then the wafer was extracted from the adhesive tape.

(Etching Treatment)

Next, the back surface (the polished plane) of the semiconductor crystalsubstrate 102 polished in the polishing treatment was dry-etched to thedepth of about 2 μm. This dry-etching treatment removed at least most ofthe damaged layer which was generated in the polishing treatment. Any ofthe following equipments can be employed in this dry-etching treatment:

(a) RIE equipment

(b) ICP equipment

The dry-etching treatment can be carried out according to the processesas follows.

(1) A protection film to RIE etching gas is formed on the surface (faceplane) of the wafer by use of resin.

(2) The wafer is placed at the RIE equipment with the back surface ofthe wafer up.

(3) The back surface of the wafer is dry-etched in the RIE equipment.

(Conditions for Carrying Out Etching Treatment)

(a) Gas employed in the treatment: CCl₂F₂

(b) Degree of vacuum: 5.3 Pa (0.04 Torr)

Here, etching is carried out to the depth of about 0.8 μm undercondition that extracting voltage (acceleration voltage) is controlledto be 800V, and dry-etching treatment is further carried out to the restof the wafer having thickness of 0.2 μm after decreasing the extractingvoltage to be 400V.

Accordingly, by carrying out etching under condition of decreasingextracting voltage (acceleration voltage) asymptotically, damaged layerformed at the back surface of the wafer through the etching treatment (afurther thinner additional physically damaged layer) can be removed orreduced.

(4) And the protection film to the RIE etching gas is removed by usingpeeling-off liquid.

For example, the dry-etching disclosed in Japanese Patent ApplicationLaid-open No. H8-274081 may be referred to as a standard of dry-etchingtreatment.

(Dividing Process)

Half cutting treatment or scribing treatment was carried out to thesurface of the wafer, and the semiconductor wafer was divided into eachchip through breaking process. Each of these processes may be carriedout according to a well-known prior art. For example, the dividingtechnique disclosed in the Japanese Patent Application Laid-open No.2001-284642 may be referred to as a standard of dividing process.

According to the processes described above, the face-down typelight-emitting diode 100 shown in FIG. 1 can be obtained.

Luminous output of the thus-obtained light-emitting diode 100 isimproved by about 20% compared with that of a conventional diode withoutcarrying out the dry-etching treatment of this embodiment. And luminousoutput of the light-emitting diode 100 having the taper part is twice aslarge as that of the conventional diode without a taper part.

In short, the light-emitting diode 100 in the embodiment 1 of thepresent invention has remarkably high luminous output owing tomultiplier effect of using GaN bulk crystal to form the crystal growthsubstrate, forming the taper part at the crystal growth substrate, andcarrying out dry-etching treatment to the polished plane and the grindedplane of the crystal growth substrate.

Modified Example and Each Optimum Condition

The first embodiment of the present invention can be modified oroptimized according to each condition as follows.

For example, an optimum depth of dry-etching is determined according tosize of the grains of the slurry used in the previous polishing process,degree of frictional force and pressure, and composition ratios of thesubstrate. But experience shows that the optimum depth of dry-etchingmay be in a range from 1 μm to 8 μm. When the depth of dry-etching iswithin this range, time for the grinding process and the dry-etchingprocess can be kept to the minimum and that is desirable inproductivity.

In the first embodiment, the semiconductor crystal substrate 102 ispreferably made of an undoped Al_(x)Ga_(1-x)N (0≦x≦1). Alternatively,the semiconductor crystal substrate 102 can be made of other Group IIInitride compound semiconductor and a semiconductor crystal such as SiC.

In the first embodiment, a semiconductor substrate a free-standinggallium nitride crystal (: GaN bulk crystal) is applied as thesemiconductor crystal substrate 102. The semiconductor crystal substrate102 does not necessarily have single-layer structure. For example, asemiconductor bulk crystal comprising Al_(x)Ga_(1-x)N (0≦x≦1) whosethickness remains in 150 μm or more after polishing and etching can bean appropriate semiconductor crystal substrate 102 to obtain the samestructure as in the first embodiment. Because the upper part of thesemiconductor crystal substrate 102 is removed in the grinding processuntil its thickness becomes 150 μm, the semiconductor crystal substrate102 may have arbitrary structure. Alternatively, a substrate in which abase layer is formed on a silicon substrate and a GaN layer is grownthereon, or an epitaxial growth substrate, can be applied as thesemiconductor crystal substrate 102. In that case, the silicon substrateand the base layer may be removed through gas etching treatment andgrinding treatment to leave only the n-type Al_(x)Ga_(1-x)N (0≦x≦1) tohave thickness of about 150 μm.

Further alternatively, thickness of the semiconductor crystal substrate102 to be left may not be necessarily limited to 150 μm. Thesemiconductor crystal substrate 102 to be left may have any thickness aslong as it is in a range from 50 μm to 300 μm. Thickness of thesemiconductor crystal substrate 102 before carrying out the grindingprocess may preferably be in a range from 250 μm to 500 μm. Morepreferably, thickness of the semiconductor crystal substrate 102 beforecarrying out the grinding process may be in a range from 300 μm to 400μm. When the thickness is too large, the grinding process takes too muchtime and that is not desirable. When the thickness is too small, thesemiconductor wafer tends to be damaged in its handling, and that is notdesirable.

Modified Example of the First Embodiment

In the first embodiment, both of the positive electrode and the negativeelectrode are formed on the surface (face plane) of the semiconductorcrystal substrate 102. Alternatively, the negative electrode may beformed on the back surface of the semiconductor crystal substrate 102,or a polished plane 102 a which is formed to have flat plane throughdry-etching and a grinded plane 102 b which is formed in a taper shapethrough dry-etching. At that time, a face-down type light-emitting diodecan be manufactured by forming the semiconductor crystal substrate 102to be an n-type substrate having excellent electric conductivity andforming the negative electrode to be a light-transparent thin-filmelectrode.

In such a face-down type light-emitting diode, for example, lightabsorption by the physically damaged layer can be suppressed in aprocess that ultraviolet light is outputted from the surface of thelight-transparent negative electrode. Accordingly, light can beefficiently extracted from the light-emitting diode through thelight-transparent negative electrode.

In short, the light-transparent electrode can be formed on the etchingtreatment plane. Because the light-transparent electrode can bedeposited (formed contacting) directly to the n-type substrate withoutusing a physically damaged layer, the etching treatment of the presentinvention may also distribute for the electrode to maintain itsexcellent ohmic characteristic.

For example, in the process for manufacturing the longitudinalconduction face-down type light-emitting diode, a light-transparentthin-film electrode is formed on the back surface of the semiconductorcrystal substrate 102 through vapor deposition treatment instead, offorming the negative electrode 140. This vapor deposition treatment ofthe light-transparent thin-film electrode may be carried out between theetching treatment and the dividing treatment described above. Wiring tothe negative electrode in such light-emitting diode may be carried outby wire-bonding as shown in the above-described patent document 1 (FIGS.1 and 4).

The present invention is also useful when the physically processed planedescribed above is formed and shaped through blasting treatment. In thefirst embodiment, the polished plane 102 a which is formed almost flatthrough dry-etching treatment and the grinded plane 102 b which isformed in a taper shape through dry-etching treatment contact with eachother at each of their edge. Alternatively, the desired roundness R(roundness obtained by chamfering) can be obtained by curving the side(edge) of these planes through blasting treatment. The physicallydamaged layer may also be formed on the physical processing planethrough such blasting treatment. By carrying out the etching treatmentin the first embodiment after the blasting treatment, almost the sameeffect as in the first embodiment can be obtained. And carrying outappropriate blasting treatment enables to shorten necessary and adequatetime for etching treatment.

Such characteristics are explained in the following second embodiment.

Second Embodiment

In a process of forming dividing grooves by applying laser irradiation,a fused and re-solidified material, which is a material of asemiconductor fused by laser irradiation heat, and a fused, scatteredand re-solidified material, which is a material fused and scattered in achamber and then adhered and solidified there, tend to be left at thesidewalls and the back surface of the device. Such fused andre-solidified material and fused, scattered and re-solidified materialmay preferably be removed through blast treatment and so on consideringexternal quantum efficiency and luminous extracting efficiency. Even byemploying such blasting treatment, however, a physically damaged layeras in the first embodiment may be formed owing to some conditions of thetreatment. Accordingly, the present invention is also useful for adevice in which the physically damaged layer is formed through blastingtreatment.

FIG. 2 is a sectional view of a face-up type light-emitting diode 200 inthe second embodiment of the present invention. As shown in FIG. 2, thelight-emitting diode 200 has structure as in a well-known face-up typelight-emitting diode, and the back surface 1 a of a semiconductorcrystal substrate 1 made of undoped GaN bulk crystal is physicallyformed through polishing treatment, laser treatment and blastingtreatment and then finished through dry-etching treatment. The polishingtreatment is, as in the first embodiment, carried out in order to reducethickness of the semiconductor crystal substrate 1. And the lasertreatment is carried out in order to form a V-shaped groove for dividingthe wafer and a proper R (roundness) on the back surface of thesemiconductor crystal substrate 1. The blasting treatment is carried outin order to remove a fused and re-solidified material and a fused,scattered and re-solidified material and to provide a proper R(roundness). And the dry-etching treatment is, of course, carried out inorder to remove the physically damaged layer left on the physicallyprocessed plane which is shaped through blasting treatment as in thefirst embodiment.

The sign 6 in FIG. 2 represents a negative electrode formed on an n-typesemiconductor 2 a and the sign 7 represents a positive electrode formedon an p-type semiconductor layer 2 b. The positive electrode 7 ispreferably a light-transparent electrode. On a lead frame 3, areflection plane 3 a formed almost in a rotation shape of secondarycurve whose plane is formed almost in a mirror plane. The semiconductorcrystal substrate 1 is adhered at the center of the inside bottom planeof the reflection plane 3 a by a light-transparent adhesive 4. Thelight-transparent adhesive 4 may be preferably made of a transparentmaterial as much as possible so as to improve external quantumefficiency. A tilt angle of a tilt plane 1 a in the light-emitting diode200 may preferably be arranged optimally in accordance with the value ofthe refractive index of the light-transparent adhesive 4. Alternatively,the tilt angle of the tilt plane 1 a is determined first and then thematerial of the light-transparent adhesive 4 may be determinedconsidering each condition such as refractive index.

In the light-emitting diode 200, luminous extracting efficiency of theback surface and the sidewalls of the semiconductor crystal substrate 1having the tilt plane 1 a is remarkably large owing to the actions andeffects of the present invention. As a result, the face-up type LED(semiconductor light-emitting device) may also provide larger externalquantum efficiency compared with the conventional device.

In short, the present invention can also be applied to a face-up typelight-emitting diode.

Third Embodiment

In the first embodiment, the taper part is formed at the semiconductorcrystal substrate 102. Alternatively, the taper part for extractinglight may be formed at the sidewall of each semiconductor layer(103-107) deposited through crystal growth to face to the surface of thewafer. The taper part deposited on formed on the side wall near thesurface of semiconductor layers functioning as a device also contributesto improve luminous extracting efficiency and external quantumefficiency. A similar taper part tends to be formed at the surface ofthe wafer when a V-shaped groove for dividing chip is formed on thesurface of the wafer. These taper parts can be formed by using, forexample, a dicing cutter. And the etching treatment (finishingtreatment) is useful for each of thus-obtained taper parts.

Such characteristics are explained in the third embodiment.

FIG. 3 is a sectional view of a face-up type light-emitting diode 1000in the third embodiment of the present invention. The light-emittingdiode 1000 comprises a sapphire substrate 1001 which is polished untilits thickness becomes about 100 μm after forming a protection film 1300.

About 0.5 μm in thickness of aluminum nitride (AlN) single crystal layer1011 is formed on the sapphire substrate 1001, and about 1.5 μm inthickness of silicon (Si) doped Al_(0.12)Ga0.88N n-type contact layer1020 having electron concentration of 5×10¹⁸/cm³ is formed thereon.

About 100 nm in thickness of silicon (Si) doped n-type clad layer 1030which has electron concentration of 5×10¹⁹/cm³ and has multiple-layerstructure comprising 38 pairs of about 1.5 nm in thickness ofAl_(0.15)Ga_(0.85)N layer 1031 and about 1.5 nm in thickness ofAl_(0.04)Ga_(0.96)N layer 1032 is formed on the n-type contact layer1020.

An emission layer 1040 which has single quantum well structure andmainly emits ultraviolet light is formed on the n-type clad layer 1030.The emission layer 1040 having single quantum well (SQW) structure isformed by depositing about 25 nm in thickness of undopedAl_(0.13)Ga_(0.87)N barrier layer 1041, about 2 nm in thickness ofundoped Al_(0.005)In_(0.045)Ga_(0.95)N well layer 1042, and about 15 nmin thickness of undoped Al_(0.13)Ga_(0.87)N barrier layer 1043 insequence.

About 40 nm in thickness of magnesium (Mg) doped Al_(0.16)Ga_(0.84)Np-type block layer 1050 having hole concentration of 5×10¹⁷/cm³ isformed on the emission layer 1040. About 90 nm in thickness of magnesium(Mg) doped p-type clad layer 1060 which has hole concentration of5×10¹⁷/cm³ and comprises 30 pairs in total comprising about 1.5 nm inthickness of Al_(0.12)Ga_(0.88)N layer 1061 and about 1.5 nm inthickness of Al_(0.03)Ga_(0.97)N layer 1062 is formed on the p-typeblock layer 1050. About 30 nm in thickness of magnesium (Mg) doped AlGaNp-type contact layer 1070 having hole concentration of 1×10¹⁸/cm³ isformed on the p-type clad layer 1060.

A light-transparent thin film positive electrode 1100 is formed on thep-type contact layer 1070 through metal deposition and a negativeelectrode 1400 is formed on the n-type contact layer 1020. Thelight-transparent thin film positive electrode 1100 comprises about 1.5nm in thickness of first layer 1110 which is made of cobalt (Co) anddirectly contacts to the p-type contact layer 1070 and about 6 nm inthickness of second layer 1120 which is made of gold (Au) and contactsto the cobalt film.

A thick film positive electrode 1200 is formed on the light-transparentthin film positive electrode 1100 by depositing about 18 nm in thicknessof first layer 1210 made of vanadium (V), about 15 μm in thickness ofsecond layer 1220 made of gold (Au), and about 10 nm in thickness ofthird layer 1230 made of aluminum (Al) in sequence.

The negative electrode 1400 having multiple-layer structure is formed bydepositing about 18 nm in thickness of first layer 1410 made of vanadium(V) and about 100 nm in thickness of second layer 1420 made of aluminum(Al) on an exposed portion of the n-type contact layer 1020.

And a protection film 1300 made of an SiO₂ film is formed on theuppermost part of the wafer. On the bottom plane (etching plane β) ofthe sapphire substrate 1001 which is treated through etching, about 500nm in thickness of reflection metal layer 1500 made of aluminum (Al) isformed through metal deposition. Alternatively, the reflection metallayer 1500 may comprises a metal such as Rh, Ti, and W, and also anitride compound such as TiN and HfN.

An etching plane α in a taper shape is formed at each sidewall of thewafer as shown in FIG. 3. When a V-shaped groove for dividing the waferis formed by using a dicing cutter, a taper part (grinded plane) isformed at the sidewalls of the wafer including the semiconductor crystallayer and the etching plane α is obtained by finishing the taper partthrough dry-etching treatment. Because the physically damaged layerwhich is formed in the V-shaped groove forming process and is left atthe taper part (grinded plane) is removed from the etching plane α,absorption of ultraviolet light can be effectively reduced. As a result,the etching plane α treated by dry-etching greatly contributes toextract light toward upside of the wafer.

The etching plane β (the bottom surface of the sapphire substrate 1001)is obtained by further dry-etching the back surface of the wafer(polished plane) which is exposed through polishing treatment. Becausethe physically damaged layer which is formed and left at the backsurface of the wafer (grinded plane) after grinding treatment is removedfrom the etching plane β, absorption of ultraviolet light can beeffectively reduced. As a result, reflectivity of the reflection metallayer 1500 can be improved effectively. Accordingly, the etching plane βtreated by dry-etching greatly contributes to extract light towardupside of the wafer.

In the wafer of this embodiment, a band gap of each semiconductorcrystal layer is maintained as large as possible by optimizing aluminumcomposition ratio of each semiconductor crystal layer. By employing suchstructure, light in near-ultraviolet region emitted by the emissionlayer can be effectively restrained from being absorbed in thesemiconductor crystal layers except for the emission layer. Accordingly,arranging band gap of each layer as in this embodiment may alsocontribute to improving external quantum efficiency of thelight-emitting diode 100.

Fourth Embodiment

FIG. 8 is a sectional view of the main portion of a light-emitting diode500 of the fifth embodiment of the present invention. As shown in FIG.8, a semiconductor substrate a is doped with silicon (Si) as an impurityand its doping concentration is about 4×10¹⁸/cm³. Owing to its functionin the light-emitting diode 500, the semiconductor substrate a is alsoreferred to as a n-type contact layer 503 hereinafter.

A crystal growth layer b comprises a Group III nitride compoundsemiconductor having multiple-layer structure. The surface of thesemiconductor substrate a comprising an n-type gallium nitride (GaN)contributes to crystal growth of the crystal growth layer b. Theopposite surface of the semiconductor substrate a (hereinafter referredto as a back surface or a polished plane) is polished and dry-etched,and a negative electrode (n-electrode c) is formed thereon.

On the semiconductor substrate a (n-type contact layer 503), 105 Å inthickness of undoped GaN n-type clad layer 504 (low-carrierconcentration layer) is formed. An active layer 505 of MQW structurecomprising 5 layers in total is formed thereon. In the active layer 505,about 35 Å in thickness of In_(0.30)Ga_(0.70)N well layer 510 and about70 Å in thickness of GaN barrier layer 520 are deposited alternately.About 50 nm in thickness of Mg-doped p-type Al_(0.15)Ga_(0.85)N isformed as a p-type clad layer 506 on the active layer 505. And about 100nm in thickness of Mg-doped p-type GaN is formed as a p-type contactlayer 507 on the p-type clad layer 506.

On the p-type contact layer 507, a light-transparent positive electrode(p-electrode 509) is formed by metal deposition. The p-electrode 509comprises about 40 Å in thickness of cobalt (Co) which directly contactsto the p-type contact layer 507 and about 60 Å in thickness of goldwhich contacts to the Co layer.

The n-electrode c is formed by depositing about 200 Å in thickness ofvanadium (V) and about 1.8 μm in thickness of aluminum (Al) or an alloyincluding Al in sequence on the back surface (etched plane) of thesubstrate. Thickness of the n-electrode c is arranged larger in order toreflect light toward upside sufficiently.

Next, a method for manufacturing the light-emitting diode 500 isexplained hereinafter. Processes and materials employed in thisembodiment are as same as those in the third embodiment of the presentinvention.

The semiconductor substrate a made of single crystal GaN was placed on asusceptor in a reaction chamber for the MOVPE treatment after its mainsurface ‘a’ was cleaned by an organic washing solvent and heattreatment. Thickness of the semiconductor substrate a was about 400 μm.Then the semiconductor substrate a was baked at about 1150° C. under H₂vapor fed at 2 liter/min. into the chamber for 30 minutes under normalatmospheric pressure.

(Growth of the N-Type Clad Layer 504)

105 Å in thickness of undoped GaN was formed as the n-type clad layer504 (low carrier concentration layer) under conditions controlled bykeeping the temperature of the semiconductor substrate a at 1150° C.,and concurrently supplying H₂, NH₃, and TMG at a flow rate of 20liter/min., 10 liter/min., and 1.7×10⁻⁴ mol/min., respectively.

(Growth of the Active Layer 505)

After forming the n-type clad layer 504, the active layer 505 of MQWstructure (shown in FIG. 8), comprising 5 layers in total, was formed.

First, about 35 Å in thickness of In_(0.30)Ga_(0.70)N well layer 510 wasformed on the n-type clad layer 504 under conditions controlled bylowering the temperature of the semiconductor substrate a to 730° C.,changing carrier gas from H₂ to N₂, keeping the supplying amount of thecarrier gas N₂ and NH₃, and concurrently supplying TMG and TMI at a flowrate of 3.1×10⁻⁶ mol/min. and 0.7×10⁻⁶ mol/min., respectively.

Next, about 70 Å in thickness of GaN barrier layer 520 was formed on thewell layer 510 under conditions controlled by raising the temperature ofthe semiconductor substrate a to 885° C., and concurrently supplying N₂,NH₃, and TMG at a flow rate of 20 liter/min., 10 liter/min., and1.2×10⁻⁵ mol/min., respectively.

By repeating these processes, the well layer 510 and the barrier layer520 were formed alternately and the active layer 505 comprising 5 layersin total (the well layer 510, the barrier layer 520, the well layer 510,the barrier layer 520, and the last well layer 510) was obtained.

(Crystal Growth of the P-Type Clad Layer 506)

Then magnesium (Mg) doped p-type Al_(0.15)Ga_(0.85)N having thickness ofabout 200 Å and Mg concentration of 5×10¹⁹/cm³ was formed as a p-typeclad layer 506 under conditions controlled by raising the temperature ofthe semiconductor substrate a to 890° C. and concurrently supplying N₂,TMG, TMA, and CP₂Mg at a flow rate of 10 liter/min., 1.6×10⁻⁵ mol/min.,6×10⁻⁶ mol/min., and 4×10⁻⁷ mol/min., respectively.

(Crystal Growth of the P-Type Contact Layer 507)

Then Mg-doped p-type GaN having thickness of about 85 nm and Mgconcentration of 5×10¹⁹/cm³ was formed as a p-type contact layer 507under conditions controlled by raising the temperature of thesemiconductor substrate a to 1000° C., changing the carrier gas to H₂again, and concurrently supplying H₂, NH₃, TMG, and CP₂Mg at a flow rateof 20 liter/min., 10 liter/min., 1.2×10⁻⁴ mol/min., and 2×10⁻⁵ mol/min.,respectively.

The processes described above are the crystal growth process of eachsemiconductor layer comprising a Group III nitride compoundsemiconductor.

(Forming the P-Electrode 509)

After the crystal growth processes described above, a photoresist layerwas then formed on the surface of the p-type contact layer 507. Theportion of the photoresist layer above the electrode forming part of thep-type contact layer 507 was then removed by patterning usingphotolithography to form a window. In short, only a portion of thep-type contact layer 507 for forming the p-electrode 509 was exposed.After establishing a high vacuum of less than 10⁻⁴ Pa vacuum order,about 40 Å in thickness of Co was deposited on the exposed portion ofthe p-type contact layer 507, and 60 Å in thickness of Au was depositedon the Co. The sample was then removed from the vacuum evaporationequipment and Co and Au laminated on the photoresist layer were removedby a lift-off process. Accordingly, the light-transparent p-electrode509 adhering to the p-type contact layer 507 was formed.

(Polishing Treatment)

Next, the back surface of the semiconductor substrate a was polished byusing a polishing machine. Diameter of grain of the slurry employed inthis polishing treatment was 9 μm, and the polishing treatment wascarried out until thickness of the semiconductor substrate a decreasedfrom 400 μm to 150 μm. Then the wafer was washed and dried. Diameter ofgrain of the slurry employed in the polishing treatment may preferablyin a range from 0.5 μm to 15 μm. When the diameter of grain of theslurry is too big, thickness of the damaged layer tends to become toolarge, which is not desirable. When the diameter of grain of the slurryis too small, the polishing treatment tends to take too much time, whichis not desirable. More preferably, the diameter of grain of the slurryis in a range from 1 μm to 9 μm.

(Etching Treatment)

Next, the back surface (the polished plane) of the semiconductorsubstrate a polished in the polishing treatment was dry-etched to thedepth of about 2 μm. This dry-etching treatment removed at least most ofthe damaged layer which was generated in the polishing treatment. Any ofthe following equipments can be employed in this dry-etching treatment:

(a) RIE equipment

(b) ICP equipment

For example, the dry-etching disclosed in Japanese Patent ApplicationLaid-open No. H8-274081 may be referred to as a standard of dry-etchingtreatment.

(Forming the N-Electrode C)

Next, a photoresist layer was formed on the entire back surface of thesemiconductor substrate a. The portion of the photoresist layer abovethe predetermined part of the n-type contact layer 503 was then removedby patterning using photolithography to form a window. In short, only aportion of the n-type contact layer 503 was exposed. After establishinga high vacuum of less than 10⁻⁴ Pa vacuum order, about 200 Å inthickness of vanadium (V) was deposited on the exposed portion of then-type contact layer 503, and 1.8 μm in thickness of Al was deposited onthe V. Then the photoresist layer was removed and the n-electrode cadhering to the semiconductor substrate a (n-type contact layer 503) wasobtained.

(Alloying Treatment)

Next, the chamber in which the resultant sample was placed was evacuatedby use of a vacuum pump, and subsequently O₂ gas was fed to the chamber,to thereby regulate the pressure of the chamber to 3 Pa. Thereafter, thetemperature of the chamber was maintained at about 550° C., and thesample was heated for about three minutes, to thereby lower theresistances of the p-type contact layer 507 and the p-type clad layer506, as well as to perform alloying of the contact layer 507 and thep-electrode 509 and alloying of the semiconductor substrate a and then-electrode c. Thus, the electrodes (the n-electrode c and thep-electrode 509) can be connected to each semiconductor layer on whichboth electrodes were deposited more firmly.

Half cutting treatment or scribing treatment was carried out to thesurface of the wafer, and the semiconductor wafer was divided into eachchip through breaking process. Each of these processes may be carriedout according to a well-known prior art. For example, the dividingtechnique disclosed in the Japanese Patent Application Laid-open No.2001-284642 may be referred to as a standard of dividing process.

FIG. 9 is a table showing each driving voltage V_(F) of thelight-emitting diode 500 of this embodiment and its modified example(light-emitting diode 500′). The light-emitting diode 500′ has the samestructure as shown in FIG. 8. The light-emitting diode 500′ has the samestructure as the light-emitting diode 500 except for that dry-etchingtreatment for dry-etching the polished plane of the semiconductorsubstrate a is not carried out in a method for manufacturing thelight-emitting diode 500′. In short, depth D of dry-etching thelight-emitting diode 500′ is 0 μm as shown in FIG. 9.

In FIG. 9, “I” represents driving electric current flown between thepositive electrode and the negative electrode of the device, and itshows electric current value which is needed for excellent luminousoutput of each light-emitting diode. As shown in the table of FIG. 9,while driving voltage V_(F) of the light-emitting diode 500 to which 2μm in depth of dry-etching is carried out is 3.5 v, driving voltageV_(F) of the light-emitting diode 500′ to which dry-etching is notcarried out is 10 v, which is larger than the driving voltage of thelight-emitting diode 500 by 6.5 v.

According to the result described above, when the n-electrode c isformed on the back surface of the semiconductor substrate a havingconductivity as in the light-emitting diode 500 in FIG. 8, for example,preferable depth D of dry-etching can be figured out to be about 2 μm.That can be also explained in actions and effects shown in FIGS. 5, 6,and 7 described above.

Although it depends on each condition such as the size of grain ofslurry, strength of frictional force and pressure, and composition ratioof the substrate, in order to provide excellent ohmic characteristicbetween the semiconductor substrate and the electrode, experiments showthat the optimum depth D of dry-etching may be in a range from 1 μm to 8μm. When the depth D of dry-etching is within this range, time forcarrying out both polishing treatment and dry-etching treatment can bereduced to minimum, and that is desirable for productivity of thedevice.

In the fourth embodiment, an n-type Al_(x)Ga_(1-x)N (0≦x≦1) ispreferable to form the semiconductor substrate a. Alternatively, thesemiconductor substrate a may be made of other Group III nitridecompound semiconductor. In the fourth embodiment, Si is doped as ann-type impurity into the semiconductor substrate a. Alternatively,n-type impurity to be doped into the semiconductor substrate a may notbe limited to Si.

In the fourth embodiment, a single gallium nitride crystal (n-type bulkGaN) is used to form the semiconductor substrate a. Alternatively, thesemiconductor substrate a is not necessarily have single-layerstructure. For example, in order to form the semiconductor substrate ato have the structure shown in FIG. 8, an n-type Al_(x)Ga_(1-x)N (0≦x≦1)which has a thickness of 150 μm or more and remains as an appropriaten-type contact layer 503 may be enough. Because the portion whosethickness is 150 μm or more is removed in the polishing process, it mayhave an arbitral structure. Accordingly, a base layer is formed on thesilicon substrate and then the n-type GaN layer may be grown thereon. Atthat time, the silicon substrate and the base layer may be removedthrough polishing treatment and it is enough to leave about 150 μm inthickness of the n-type Al_(x)Ga_(1-x)N (0≦x≦1).

Here, thickness of the n-type contact layer to be left is notnecessarily limited to 150 μm described above. Alternatively, thicknessof the n-type contact layer to be left may be arbitral if it is in arange from 50 μm to 300 μm. Thickness of the semiconductor substrate abefore carrying out polishing process is preferably in a range from 250μm to 500 μm. More preferably, its thickness may be in a range from 300μm to 400 μm. When the thickness is too large, polishing process takestoo much time, and that is not desirable. When the thickness is toosmall, the semiconductor wafer tends to be damaged while it is handled,and that is not desirable.

In the fourth embodiment, the p-electrode 509 is formed before polishingprocess is carried out. Alternatively, the p-electrode 509 may be formedthrough similar process of forming the n-electrode c, or may be formedafter etching process.

Alternatively, the n-electrode c may be formed after carrying out heattreatment (alloying process of the p-electrode 509). At that time, heattreatment is not carried out to the n-electrode c deposited on thesemiconductor substrate a, and practically the n-electrode is notalloyed.

In the fourth embodiment, the p-electrode 509 has light-transparency.Alternatively, the n-electrode c may have light-transparency.

In the fourth embodiment, the active layer has MQW structure.Alternatively, the active layer may have SQW structure or single-layerstructure which does not have quantum-well structure.

Fifth Embodiment

Other embodiment of the present invention will next be described. Alight-emitting diode 610 which comprises plural layers made of group IIInitride compound semiconductor formed on a sapphire substrate 600 isformed as shown in FIG. 10A. A p-electrode 620 is formed on thelight-emitting diode 610, and a pasting board 650 is adjusted to thep-electrode 620. Next, as shown in FIG. 10B, the sapphire substrate 600is polished and removed by using the pasting board 650 as a holdingmember hold-back material??). Then a damage layer 630 is formed in theGroup III nitride compound semiconductor layer, which is the bottomlayer in the light-emitting diode. The damage layer 630 is etched in aprocess similar to that in the fourth embodiment. After the etchingtreatment, an n-electrode 640 is formed on the etched Group III nitridecompound semiconductor layer. The pasting board 650 functions as aholding member while the sapphire substrate 600 is polished. As aproduct, the pasting board 650 can be used as a heat sink of thelight-emitting diode 610, a metal reflection plate which reflects lightto the n-electrode 640 side, or a fixing member of the light-emittingdiode 610. Further, the pasting board 650 can be exfoliated afterpolishing process of the sapphire substrate 600. In the fifthembodiment, n-layer is deposited on the sapphire substrate 600 beforethe p-layer. Alternatively, the p-layer may be deposited before then-layer. The p-layer deposited on the sapphire substrate 600 beforedepositing the n-layer can be activated by carrying out heat treatmentafter polishing the sapphire substrate 600.

The present invention can be applied to manufacture such light-emittingdiode.

The present invention can be widely applied to a semiconductor device inwhich an electrode is formed directly on a semiconductor substrate. Sucha semiconductor device may include a light-emitting semiconductor lasersuch as a semiconductor laser (LD) and a light-emitting diode (LED), andalso include a light-receiving device and a pressure sensor. The presentinvention may not restrict concrete function and structure of thosesemiconductor devices, and that enables to apply the present inventionin remarkably large field.

INDUSTRIAL APPLICABILITY

The present invention can be applied to a light-emitting diode havingcomparatively shorter wavelength and emission region at least a portionof whose luminous spectrum is less than 470 nm. Accordingly, the presentinvention can also be applied to a luminous device having emissionregion in visible light region.

Further, owing to its actions and effects, the present invention canalso be applied to a light-receiving semiconductor device.

The present invention may not restrict any condition such as crystalgrowth condition, composition, and deposition structure of thosesemiconductor devices.

The present invention is also very useful to a short-wavelength luminousdevice whose luminous wavelength is in ultraviolet region. Suchshort-wavelength luminous device may be applied in photochemistry fieldusing photoexcitation catalyst, in illumination filed used to excitephosphor, or in bio-related field represented by a light trap, and itcan be applied to, for example, a black-light lamp consisted in afluorescent lamp.

While the present invention has been described with reference to theabove embodiments, the present invention is not limited thereto, but maybe modified as appropriate without departing from the spirit of theinvention.

The entire disclosures and contents of Japanese Patent Application Nos.2004-112796 and 2003-202240, from which the present invention claimsconvention priority, are incorporated herein by reference.

1. A method for fabricating a light-emitting diode of a surface emittingtype in which a semiconductor layer is deposited on a crystal growthplane of a crystal growth substrate, comprising steps of: a shapingprocess for forming at least one of an output plane and a reflectionplane which contributes to luminous output of the device throughpolishing treatment, dicing treatment, and blasting treatment from theback surface of said crystal growth substrate; and a finishing processfor finishing said at least one of output plane and said reflectionplane by further carrying out etching treatment.
 2. A method forfabricating a light-emitting diode according to claim 1, wherein saidshaping process comprises a taper part forming process for forming ataper plane, which inclines to said crystal growth plane of said crystalgrowth substrate, at least as a portion of said output plane or at leastas a portion of said reflection plane.
 3. A method for fabricating alight-emitting diode according to claim 2, wherein at least a portion ofsaid taper part forming process comprises of a process for forming anapproximately V-shaped dividing groove which divides a semiconductorwafer comprising plural light-emitting diodes into each of saidlight-emitting diode.
 4. A method for fabricating a light-emitting diodeaccording to claim 1, wherein peak luminous wavelength of saidlight-emitting diode is less than 470 nm.
 5. A method for fabricating alight-emitting diode according to claim 1, wherein said crystal growthsubstrate is formed by using Al_(x)Ga_(1-x)N (0≦x≦1) or silicon carbide(SiC).
 6. A light-emitting diode of a surface emitting type in which asemiconductor layer is deposited on a crystal growth plane of a crystalgrowth substrate, wherein said crystal growth substrate comprises atleast one of an output plane and a reflection plane which contributes toluminous output of the device through a physical shaping process such aspolishing treatment, dicing treatment and blasting treatment, and aphysically damaged layer which is formed on the surface of at least oneof said output plane and said reflection plane and remains owing tofriction and shock generated in said shaping process is removed.
 7. Alight-emitting diode according to claim 6, wherein a metal layer whichhas light-transparency to transmit light to the luminous extracting sideof said device is formed on said output plane.
 8. A light-emitting diodeaccording to claim 6, wherein a metal layer which reflects light to theluminous extracting side of said device is formed on said reflectionplane.
 9. A light-emitting diode according to claim 6, wherein saidcrystal growth substrate is formed by using Al_(x)Ga_(1-x)N (0≦x≦1) orsilicon carbide (SiC).
 10. A light-emitting diode according to claim 6,wherein a taper plane which inclines to said crystal growth plane ofsaid crystal growth substrate is formed at least as a portion of atleast one of output plane or at least as a portion of said reflectionplane.
 11. A light-emitting diode of a surface emitting type in which asemiconductor layer is deposited on a crystal growth plane of a crystalgrowth substrate, comprising: a taper plane which inclines to saidcrystal growth plane of said crystal growth substrate which is formed atleast at a portion of the sidewall of said light-emitting diode, whereinsaid taper plane is exposed to the surface side of said light-emittingdiode at which a semiconductor crystal layer and a positive electrodeare formed, and a physically damaged layer which is formed on thesurface of said taper plane and remains owing to friction and shockgenerated in said taper part is removed.
 12. A light-emitting diodeaccording to claim 10 which is fabricated by dividing a semiconductorwafer comprising plural light-emitting diodes into each of saidlight-emitting diode, comprising: a taper plane at least at a portion ofthe sidewall of said light-emitting diode, wherein said taper plane is aportion of the plane of an approximately V-shaped dividing groove whichdivides the semiconductor wafer into each of said light-emitting diode.13. A light-emitting diode according to claim 6, wherein the peakluminous wavelength of said light-emitting diode is less than 470 nm.14. A method for forming an electrode in which an electrode is formed ona polished plane of a conductive semiconductor substrate which comprisesa Group III nitride compound semiconductor and has already been polishedcomprising a step of: etching process for carrying out dry-etchingtreatment to said polished plane of said semiconductor substrate beforeelectrode forming process for forming an electrode on said polishedplane of said semiconductor substrate.
 15. A method for forming anelectrode according to claim 14, wherein said semiconductor substrate isformed by using an n-type Al_(x)Ga_(1-x)N (0≦x≦1).
 16. A method forforming an electrode according to claim 14, wherein depth of removingsaid polished plane through said dry-etching treatment is in a rangefrom 0.1 μm to 15 μm.
 17. A method for forming an electrode according toclaim 16, wherein depth of removing said polished plane through saiddry-etching treatment is in a range from 0.2 μm to 8 μm.
 18. A methodfor fabricating a light-emitting diode according to claim 2, whereinpeak luminous wavelength of said light-emitting diode is less than 470nm.
 19. A method for fabricating a light-emitting diode according toclaim 2, wherein said crystal growth substrate is formed by usingAl_(x)Ga_(1-x)N (0≦x≦1) or silicon carbide (SiC).
 20. A light-emittingdiode according to claim 7, wherein a metal layer which reflects lightto the luminous extracting side of said device is formed on saidreflection plane.